How does the bit mapping (pin or port) of the configurable submodules of the H08 IO-Link master work?

This question is frequently asked, as most customers are only familiar with pin-based data mapping. In our IO-Link masters of HW generation 8, however, we also offer the option of port-based pin mapping.

The two options can be selected and the corresponding assignment in the byte is explained in the respective configuration instructions. To avoid misunderstandings, the option is summarized here.

The first step is to set the mapping in the header module.
Pin or port based. The data mapping is referred to here as the layout.
Screenshot 01 shows an example of the device configuration in the TIA Portal.

(Screenshot 01)

The hardware catalog offers the option of configuring IO modules in the device configuration.

In screenshot 02, the module "Input Pin 2/Port 4_7" and "Output Pin 2/Port 4_7" is configured as an example.
Here is an explanation of how the labeling of these modules in the GSDML file is to be understood:

The " / " between the label, means "Or". It is often wrongly interpreted here that only the respective pin of max. 4 ports is supported!


(Screenshot 02)

These are the two options from Screenshot 1.
PIN based means; all pin 2 or pin 4 on one byte.
PORT based means pin 2 and pin 4 of the selected ports on one byte.


Screenshot from the configuration instructions of the respective product.